Summary of "Overview of VLSI Design Flow - IV"

This lecture (Lecture 6) continues the discussion on the VLSI Design Flow, focusing specifically on the Physical Design phase, which follows the previously covered Logic Synthesis phase in the RTL-to-GDSII flow.

Main Ideas and Concepts

Physical Design Overview
- Physical Design converts a netlist (output of Logic Synthesis) into a layout represented as GDSII (geometrical patterns on masks for IC fabrication).
- Inputs to Physical Design:
  - Netlist: From Logic Synthesis.
  - Technology Library: Liberty format files describing timing and logical characteristics.
  - Physical Library (LEF files): Abstract physical information of standard cells (bounding boxes, pin locations, resistance, etc.).
  - Constraints (SDC files): Design goals such as timing, maximum frequency, and signal behavior.
  - Floorplan Information: Layout size, shape, aspect ratio, and predefined locations for macros and IO cells.
- Output: Final layout with placed standard cells/macros and routed interconnects, maintaining netlist connectivity.
Major Tasks in Physical Design
- Chip Planning (Floorplanning)
  - Partition design into blocks or subsystems.
  - Decide locations and shapes of large blocks (macros, memory, CPU cores).
  - Allocate rows for standard cells.
  - Plan IO cell placement, often at the periphery.
  - Power planning: design Power Delivery Network (PDN) ensuring voltage drop is within limits.
  - Consider congestion to avoid routing and timing issues.
- Placement
  - Determine exact locations of millions of standard cells within allocated rows.
  - Highly automated due to scale.
  - Objectives:
    - Minimize total wire length by placing connected cells close.
    - Meet timing constraints by placing critical path cells close.
    - Avoid overcrowding to reduce routing congestion.
- Clock Tree Synthesis (CTS)
  - Design and route the clock distribution network.
  - Deliver clock signal to all sequential elements with minimal skew.
  - Objectives:
    - Minimize clock skew (difference in clock arrival times at flip-flops).
    - Minimize power dissipation in the clock network (can be up to 40% of total power).
    - Achieve a symmetric clock tree topology to reduce skew.
    - Insert clock gating to reduce unnecessary clock activity and save power.
- Routing
  - Connect all nets except clock and power nets (already routed).
  - Objectives:
    - Minimize wire length, routing area, via count, delay.
    - Increase maximum operable frequency.
  - Routing is split into two steps:
    - Global Routing: Planning routing paths through coarse rectangular regions (global bins).
    - Detailed Routing: Actual wire layout on metal layers and vias within global bins.
- Engineering Change Order (ECO)
  - Controlled incremental fixes or changes after routing.
  - Avoid introducing new bugs.
- Tape Out
  - Final GDSII file is sent to the foundry for mask generation and fabrication.
  - Marks the end of design implementation.
Additional Details
- Between major Physical Design steps, optimization steps are performed:
  - Buffer insertion on long wires to improve delay.
  - Cell resizing to meet power/performance goals.
  - Minor placement or routing tweaks to improve timing or reduce congestion.
  - These changes are incremental to avoid large disruptions.
- Verification is essential throughout:
  - Timing, power, signal integrity, design rule checks.
  - Iterations and feedback loops between steps are common to fix issues.
- Design Closure:
  - Achieving all design goals simultaneously is challenging.
  - Iterative flow with feedback loops between chip planning, placement, CTS, routing, and sometimes back to Logic Synthesis.
  - Reducing iterations is a key goal, aided by better estimation techniques and machine learning.
  - The Physical Design flow is not strictly linear; loops and iterations are necessary to refine the design.
Next Steps
- After implementation, verification and design-for-testing (DFT) are crucial.
- These will be covered in the next lecture.

Detailed Methodology / Steps in Physical Design Flow

Inputs to Physical Design:
- Netlist (from Logic Synthesis)
- Technology Library (Liberty format)
- Physical Library (LEF format)
- Constraints (SDC format)
- Floorplan information (size, shape, macro and IO locations)
Physical Design Major Steps:
1. Chip Planning / Floorplanning
  - Partition design into blocks.
  - Decide macro locations and shapes.
  - Allocate rows for standard cells.
  - Plan IO cell placement.
  - Design power delivery network (PDN).
  - Consider congestion and timing impact.