Summary of "Лекция 100. D-триггер"
Main ideas / concepts covered
- The lecture explains the operation of D-trigger (D flip-flop) in two variants:
- Static (level-sensitive) D-trigger
- Dynamic (edge-triggered) D-trigger
- It builds the explanation using known behavior of RS triggers and dynamic retriggering (clocked) behavior.
- Core goal: ensure that the trigger updates its output only at specific timing events—either during a clock level (static) or on a clock edge (dynamic).
Static D-trigger (level-sensitive) — operation and lesson
What is added / how it’s built
- A static D-trigger is presented as an improvement over a simpler clocked element by adding an inverter to the D input to avoid “collisions” when set/reset conditions arise simultaneously.
- The input D is applied:
- to one coincidence path directly
- to another coincidence path inverted
- Outputs:
- Q
- (\overline{Q}) (not Q), which is always the inverse of Q due to correct input selection.
Clock behavior and “storage mode”
- The trigger has an input C (clock).
- When C = 0:
- coincidence circuits block passage of set/reset control signals
- therefore the flip-flop remains in storage mode (keeps its previous state)
Key timing rule (when output follows D)
- Typical operating assumption:
- D changes much more slowly than C
- Under that assumption:
- when C is high (active level), the output updates according to D
- effectively, Q repeats D while C allows propagation
Weakness (why it can misbehave)
- Problem scenario:
- D changes during the active time of C (i.e., while C is a “wide pulse” / level is high)
- Result:
- because it responds to the level of C, internal recomputation occurs throughout the clock pulse
- thus with a sufficiently wide C pulse, changes in D during C can cause undesired/incorrect output timing
- Summarized weakness:
- a static trigger updates inadequately “during the C pulse itself”
- it is called static because it depends on the signal level at input C, not its edge
Dynamic D-trigger (edge-triggered) — method and why it fixes the weakness
Concept: convert two static triggers into an edge-triggered device
- The dynamic trigger is described as a system of:
- two static triggers
- each has a drawback when output can change during the clock pulse
- Combined properly, the drawbacks cancel, producing the desired behavior:
- output changes occur only at the front/edge of C
Structure (described as two triggers clocked by one C)
- Use two static triggers, both controlled by the same clock signal C, with one of them driven by an inverted version:
- an inverter generates (C’) (inverted clock) for the first/second trigger path (as described in the lecture)
- The output of the first trigger becomes the input to the second trigger.
Qualitative operation
- When C = 0:
- an enabling/blocking signal prevents the second trigger from responding
- the first trigger may “repeat” inputs based on its gating state (as described qualitatively)
- When the clock edge arrives (C changes state):
- due to the inverted clock and gating, the first trigger is blocked at the output
- its last stored state is transferred into the second trigger
- the second trigger is opened so it captures that transferred value
- After capture, the second trigger returns to storage.
Timing rule achieved
- Fundamental result explicitly stated:
- the change in the output signal coincides with the front of the C pulse
- Therefore:
- the output is determined only on the edge (rising edge in the described symbol convention)
- not by the position of D changes during the clock level
Symbol / definition emphasized
- Dynamic D-trigger notation includes:
- D as data input
- C as clock input, marked with a front/edge indicator
- The lecturer states the trigger responds to the rising edge of C.
- If C were fed through an inverter, it would effectively trigger on the falling edge (alternate behavior described).
Practical implementation mentioned
- Common chip implementation:
- K-155TM2, described as containing:
- two dynamic identical triggers
- each triggered on the rising edge
- K-155TM2, described as containing:
- Additional chip property:
- the TM2 microcircuit has set/additional control signals to enable or disable the trigger
- these signals have priority over D
- It is described as a complex trigger:
- behaves like an RS trigger + D trigger + dynamic (edge-triggered) behavior
Instructional / step-like methodology embedded in the explanation
Static D-trigger evaluation (conceptual procedure)
- Assume input signals C (clock) and D (data).
- Check clock level:
- If C = 0 → coincidence logic blocks → Q holds previous state
- If C allows passage (typical: C active/high) → Q updates to reflect D
- Verify timing safety condition:
- If D changes much more slowly than C, output timing is “correct” and predictable.
- If D changes while C is active (especially with wide C pulses) → static trigger may update undesirably during the pulse.
Dynamic D-trigger evaluation (conceptual procedure)
- Treat it as two static triggers in cascade with inverted clock feeding and gating.
- Determine where output updates occur:
- Output Q updates only when C has an active edge (rising edge as stated).
- During C level portions (after the edge and before the next edge):
- output remains in storage mode
- Any changes of D during the clock level do not change the output until the next relevant edge.
Speakers / sources featured
- No explicit individual speaker name is provided; the content appears to be delivered by an unnamed lecturer (“Let me remind you… Thank you for your attention.”).
- Source reference: the lectured-on topic references the RS trigger, the previously discussed RTRGer, and the practical IC K-155TM2.
Category
Educational
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