Did China just beat Intel?

Technological Concepts & Key Findings

• EUV-access divide in semiconductor manufacturing: The video depicts China’s disadvantage as being cut off from EUV lithography, then asks how large the real manufacturing gap is.
• Chip examined: Huawei’s newest flagship phone uses the HiSilicon Kirin 9030 (manufactured by SMIC on a 3rd-gen 7nm-class process called N+3).
• Measurement method: The analysis comes from a teardown workflow:
  • STEEL (SemiAnalysis Teardown Engineering and Evaluation Lab) physically tears down advanced chips and uses tools like electron microscopy to extract physical parameters.
  • The video reports STEEL can provide measured data such as wire pitch, transistor density, and cross-sections used for reverse engineering.

Headline Numbers (Physical Design Metrics)

Metal pitch (smallest wiring feature)

• Kirin 9030 / SMIC N+3: minimum metal pitch ~32.5 nm
• Intel 18A (“Pandalake”): metal pitch can be ~32 nm at M0, but Intel’s overall design also uses a looser metal pitch for high-performance cell layers (noted as ~36 nm in those areas)
• Comparison baseline chip: MediaTek Helio G99 (on TSMC N6), with smallest metal pitch ~40 nm

Transistor density comparison

• SMIC N+3: ~113 million transistors/mm²
• TSMC N6: ~108 million transistors/mm²
• Conclusion: SMIC’s DUV-based N+3 matches or slightly exceeds N6-class density, even without EUV.

How SMIC Achieves EUV-like Density Without EUV

The video describes two main “workarounds,” each with tradeoffs.

1) Multi-patterning (DUV “stretching”)

• Without EUV’s near-single-shot printing, SMIC uses self-aligned double patterning (SPACER-based) and tighter requirements use quadruple patterning.
• Tradeoffs emphasized:
  • more masks
  • more alignment steps
  • more opportunities for error
  • higher cost
  • lower yields

2) DTCO (Design Technology Co-Optimization)

• Instead of treating chip design and process separately, DTCO jointly optimizes them by changing cell/layout details.
• Examples of DTCO tactics mentioned:
  • layout squeezing (area reduction)
  • fewer fins per transistor
  • gate contact placement directly atop the active gate
  • shrinking isolation gaps between neighboring cells
• Tradeoffs emphasized: transistors can become more delicate and harder to model, affecting robustness.

Why Density ≠ Performance/Efficiency

• Tighter wires increase density, but don’t automatically deliver speed or power efficiency.
• After the end of Dennard scaling (described as mid-2000s), the video argues that shrinking isn’t “free” for power and performance.
• Observed consequence for the Kirin 9030:
  • relatively dense, but performance is described as roughly equivalent to ~3-years-ago Android flagships
  • efficiency gap is larger than speed gap

Example used: Huawei vs. Apple

• Apple’s small efficiency cores (E-cores) are said to outperform Huawei’s big prime core on integer performance while consuming ~1W vs ~4.5W (as claimed in the subtitles).
• Additional comparisons referenced:
  • Huawei big-core performance-per-clock vs Arm Cortex-X2 (2021)
  • Apple M1 (2020) claimed ~35% faster per clock at similar power
• Bottom line: N+3 improves the “density axis,” but not the “physics/efficiency axis.”

Comparison to Intel 18A: “Headline Pitch” vs Real Competitiveness

• On paper: Intel 18A can reach ~32 nm M0 metal pitch, similar to SMIC N+3’s 32.5 nm.
• Caution from the video: Intel’s effective high-performance cell design uses looser pitch (~36 nm) in those areas—often beneficial for cost/yield, depending on design constraints.
• Transistor density advantage: Intel 18A is said to clearly outclass N+3 on density.
• Backside Power Delivery (BSPD) explanation:
  • Intel 18A’s backside power delivery can permit lower front-side metal pitch because power connections come from the backside, altering how pitch translates into real design outcomes.

Why China Is Still a Meaningful Threat (Even If Behind)

• The video argues that being “a few years behind” is not the same as being “stuck.”
• Future SMIC improvements are described as plausible but cumulative and challenging without EUV:
  • N+4 could target TSMC N5-class density (on density metrics)
  • N+5 could target Intel 18A-class density via backside power delivery
• Major warning: stacking mitigations without EUV likely makes nodes slower, more expensive, and less forgiving each generation (the “steeper wall” analogy).
• Strategic shift highlighted: SMIC learning is spreading by licensing N+2 and N+3 to other domestic fabs.
  • If process knowledge scales into an AI-accelerator ecosystem, sanctions could become less effective because the bottleneck becomes an entire domestic supply/production ecosystem, not a single fab.

Review / Guide / Tutorial Elements

• Not a conventional product review, but a deep technical tutorial-like explanation covering:
  • how wire pitch and density are measured via chip teardowns
  • how multi-patterning and DTCO work in practice
  • how to interpret metal pitch numbers (not directly equal to competitiveness)
  • how to compare nodes across vendors using consistent measurement methods
• Reference for deeper dive (article):
  • The speaker promotes a SemiAnalysis TechInsights article (described as the “full process flow” / deeper breakdown), suggesting the video is a first public report out of STEEL.

Main Speakers / Sources (as Stated or Implied)

• SemiAnalysis / STEEL lab (source of teardown measurements): STEEL (SemiAnalysis Teardown Engineering and Evaluation Lab)
• Video host/author (implied): a narrator associated with SemiAnalysis (mentions “I put the link…” and “this is the first public report out of Steel”)
• Mentioned industry/entities: SMIC, Huawei, TSMC, Intel, Apple, Qualcomm, MediaTek
• Chip models mentioned: Kirin 9030 and Helio G99