Agentic AI and Why Everyone Wants CPUs Again

Summary

At a Design Automation Conference keynote, semiconductor analyst Ian Cutress argues that the rise of agentic AI could renew demand for CPUs. Unlike a simple chatbot interaction, an agent workflow may repeatedly call search systems, databases, code, and other tools. Those tools often run on CPUs, while specialized solvers may use GPUs or other accelerators.

CPU requirements for AI agents remain unknown

A central challenge is that vendors cannot yet say how many CPU cores, how much memory, or what CPU-to-GPU ratio a given number of agents will require. The answer depends on the workload, industry, tools used, and how many times an agent repeats its workflow. Since AI models and agent software are changing quickly, it is difficult to optimize hardware or build specialized chips for a stable workload.

Cutress cautions that the CPU powering a GPU system may not be the best choice for running agents’ tool workloads. Some deployments may therefore need separate processor capacity alongside GPU racks. But the right balance is not yet established, and forecasts of explosive CPU demand should be viewed in light of the fact that they often come from companies selling processors.

Processor platforms discussed

The keynote surveys four broad server-CPU options:

• AMD EPYC Venice: A chiplet-based design with high-core-count configurations. Its disaggregated design could make it easier to add features such as different memory support.
• Intel Xeon: Intel’s lineup offers performance-focused and efficiency-focused core designs, with high-density configurations among the roadmap plans discussed.
• Arm AGI CPU: Arm’s own Neoverse-based processor, developed for Meta, represents Arm’s move from supplying CPU IP toward producing a complete processor.
• Nvidia Vera: Nvidia’s Arm-based CPU is designed for AI systems and racks, with NVLink providing high-speed connectivity. Cutress also discusses the possibility that Nvidia may offer an x86-based option, since some customers have existing x86 software stacks.

The talk does not establish a clear winner between x86 and Arm. Software compatibility, optimization, licensing costs, and customers’ existing infrastructure all matter. Cutress speculates that Nvidia’s future CPU choices could also be influenced by its Arm licensing arrangements, with x86 or RISC-V among possible alternatives.

Packaging, memory, and system design

As processors and accelerators grow more complex, they are moving beyond conventional packaging toward 2.5D and 3D integration, chiplets, and stacked components. That shift creates new supply-chain demands and makes thermal management, power delivery, signaling, testing, and mechanical reliability more difficult.

The keynote highlights several related trends:

• More interest in high-bandwidth memory and other memory placed close to compute.
• Possible use of stacked LPDDR and, further out, high-speed flash in processor packages.
• Greater importance of optical and other high-speed interconnects.
• Potentially separate processor racks to handle AI-agent tools around GPU-heavy systems.
• Wafer-scale designs as an extreme approach, with major challenges in cooling, power delivery, and external I/O.

Cutress notes that glass substrates attract significant attention but are still in the research and development stage, rather than an imminent mass-market solution. He also emphasizes that advanced packaging does not eliminate the need for careful testing of individual dies before assembly.

EDA, agents, and advanced transistor design

For electronic design automation (EDA), the opportunity is to move beyond tools that merely identify problems and toward agents that can help with scheduling, validation, verification, and design exploration. But dependable results and controlled costs are essential: poorly designed agent workflows could consume substantial resources without delivering useful outcomes.

Advanced packaging and 3D transistor structures also require EDA tools and foundry process design kits (PDKs) to account for thermal and mechanical constraints during design, not as an afterthought. Cutress points to early progress in tools for 3D placement and routing, while warning that much more work is needed.

He discusses IBM’s complementary field-effect transistor (CFET) research and Huawei’s “logic folding” concept as examples of increasingly vertical design approaches. His broader point is that transistor stacking and 3D integration raise new questions about density, heat, and design-tool support.

Moore’s law and alternative computing approaches

Cutress argues that “Moore’s law” can mean different things, such as transistor density, transistors per package, cost per transistor, or performance. Using transistors per package as the measure, he says growth continues through chiplets and advanced packaging, even as scaling becomes more complicated.

In the Q&A, he says specialized architectures and low-power approaches—including low-voltage designs, logarithmic arithmetic, and neuromorphic or other unconventional computing—may serve particular functions. He sees these more as potential accelerators that complement conventional digital systems than as immediate replacements.

Reviews, guides, and resources mentioned

• No product review or step-by-step tutorial is presented; this is a technology-analysis keynote.
• Cutress recommends attending Dr. Huimin Bu’s IBM 7A/CFET presentation at the conference.
• He mentions a roughly 25-minute TechTechPotato video on IBM 7A and monolithic CFETs, which explains the process and structure.
• He cites Cadence’s presentation on AI tools for 3D placement and routing as an example of progress in EDA.
• He recommends work by Austin Lyons of ChipStrat, including the Semi Dope podcast, and mentions Vic Saker.
• He refers to an earlier interview with AMD CTO Mark Papermaster about combining electrical and optical functions in chips.

Main speakers and sources

• Ian Cutress — keynote speaker and primary source of the analysis.
• Bryan Fuller — introduced Cutress.
• Audience members — asked questions about workload sizing, engineering education and tools, Nvidia’s architecture options, and low-power computing.
• Companies and technical sources discussed — AMD, Intel, Arm, Nvidia, Cadence, IBM, Huawei, Broadcom, and Cerebras.