Hardware Design with GPT-6: Schematic, PSpice & PCB

Overview

The video explores whether AI can meaningfully assist embedded hardware development, focusing on a practical example rather than relying on AI entirely. An AI-assisted workflow is used to design a buck converter for an embedded context, but the presenter emphasizes that engineering verification and corrections are still required, particularly for safety-critical systems (e.g., automotive/defense).

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Target Design Specifications

• Input: 12 V
• Output: 5 V
• Max load: 1 A
• PCB: 4-layer board

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AI-Assisted Design Steps (Codex + Supporting Tools)

1) Requirements intake + error checking

• The presenter provides detailed specifications to Codex and asks for validation.
• Codex writes detailed requirements and proposes designs around them, but the presenter decides what to accept.

2) Component selection using TI buck converter IC research

• Codex searches Texas Instruments (TI) buck converter ICs and proposes three candidate ICs, including reasoning.
• The presenter selects TI TPS54360, citing:
  • Fit to the requirements
  • TI’s comprehensive design documentation
  • Availability of a PSpice simulation model

3) Passive/part selection using datasheet equations

• Codex selects key passive components using a datasheet-equation approach.
• The selection includes checks beyond nominal values, especially:
  • MLCC effective capacitance under DC bias (not just nominal capacitance)
• The presenter stresses that showing equations is not enough—the engineer must verify:
  • correct application of datasheet terms
  • component rating compatibility
  • equation correctness

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PSpice Simulation + Automated Report Interpretation

• Codex builds the circuit and runs PSpice simulation using the selected values.
• The simulation output includes an AI-generated report with:
  • graphs
  • tables
  • descriptive text
• This is considered valuable because manually capturing waveforms and building documentation is often tedious.

Simulation failures and diagnosis

Two tests initially failed:

• Load step test
• Output voltage ripple

The presenter diagnoses the cause using control-loop metrics:

• Key clue: frequency response
  • crossover frequency ~ 1.5 kHz
  • phase margin close to ~100°

Interpretation:

• The compensator is likely too conservative.
• “More phase margin” isn’t always better—it can reduce bandwidth and slow response to load changes.

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Compensator Redesign (Retuning for Bandwidth)

• The presenter retunes the feedback compensator to increase controller bandwidth while maintaining sufficient stability margin.
• After retuning:
  • Load step test passes
  • Ripple test still fails, with partial improvement:
    • ripple generally meets requirements
    • but peak-to-peak occasionally increases
• The presenter compares before/after loop response:
  • bandwidth increases visibly
  • phase margin decreases slightly but remains reasonable
  • response improves across load conditions

The ripple peak issue is flagged as needing deeper investigation, but the video primarily demonstrates the workflow rather than fully resolving every detail.

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AI-Assisted Schematic + PCB Design (EasyEDA)

Schematic generation

• After finalizing circuit values, the schematic is created in EasyEDA.
• AI:
  • places IC/capacitors/inductors
  • wires neatly
  • adjusts footprints and ground-side widening
• The presenter notes the schematic style may differ from typical human conventions, but it could be improved with better prompting/examples.

PCB layout generation and required human intervention

AI handles initial PCB tasks:

• clearance setting
• component fitting/placement
• generating a finished-looking board

However, the presenter identifies multiple practical issues requiring engineering judgment:

• pads placed too close together
• silk screen adjustments required
• critical buck-converter placement concerns:
  • switching node routing distance should be minimized because current changes rapidly
• placement still not adequate:
  • switching-node layout not optimal (components too far apart)
  • diode orientation/rotation needed
• even following datasheet guidance, AI still produced layout concerns

The presenter requests additional AI revisions via a list of amendments:

• AI redraws placement from scratch
• the presenter stops because results still weren’t acceptable

Conclusion: an engineer must intervene for critical physical layout and EMI/current-loop considerations.

Next steps taken in the workflow

• critical parts are installed manually from that point
• final review is performed and the board is ordered
• testing is planned, with results to be shared later

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Cost / Runtime / Usage Notes

• AI runtime for the workflow: ~10 hours 16 minutes
• Total time including checking/revising and normal work: ~23 hours
• Token usage: ~422 million tokens (cost estimated from API pricing)
• The presenter notes that even if costs decrease as AI improves, trust and verification remain distinct from “AI-generated correctness.”

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Key Takeaways

AI can accelerate:

• part selection from datasheets and vendor materials
• circuit simulations
• documentation/reporting
• starting schematic and PCB drafts

But engineers still must:

• verify equations and component ratings
• interpret simulation results and redesign compensation
• validate PCB layout against real-world constraints (placement, switching-node routing, pad/silk tolerances)
• bridge the gap between simulation and real hardware variability (noise, component tolerances, temperature effects)

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Main Speakers / Sources

• Presenter: the video’s narrator/creator (uses Codex + EasyEDA + PSpice workflow; refers to their actions using “I”).
• Primary referenced technical source: Texas Instruments (TI) datasheets/design documentation, including the PSpice model for TPS54360.