AMD Zen 6 Architecture (EPYC "Venice") - Full Press Deck | DEEP DIVE

Summary

Brent Justice walks through AMD’s Zen 6 architecture slides, which accompany the EPYC 9006 “Venice” server processors. The details and configurations shown are for server CPUs. They offer clues about architecture that may later appear in desktop Ryzen processors, but do not establish desktop models, clock speeds, cache sizes, or core counts.

Architectural changes highlighted

• Larger and more capable core resources: Zen 6 increases the operation cache, return-address stack, schedulers, load/store queues, and reorder buffer. The slides also describe improved operation fusion and lower branch-misprediction latency.
• Front-end and execution improvements: AMD describes expanded branch-prediction capacity, up to three prediction windows per cycle, and delivery of up to 18 operations per cycle. Integer execution resources and the execution window are also larger.
• More data throughput: The presentation lists two stores per cycle, expanded load and store queues, and greater support for parallel data transfers and outstanding memory operations.
• New or expanded instruction support: Zen 6 adds full AVX-512 FP16 support and bit-matrix-multiply instructions. The number of VNNI INT8 execution pipes doubles from two to four. Other AVX-512 capabilities, including several existing floating-point paths, are described as largely unchanged.
• Server cache and core configurations: AMD’s EPYC comparison shows up to 12 cores per complex for full Zen 6, compared with eight for Zen 5. Zen 6C, the compact server core, is shown scaling from 16 to 32 cores per complex, with more L3 cache. These figures apply to EPYC configurations, not confirmed desktop products.

The slides also discuss server-focused features such as confidential computing, SMT protection, performance monitoring, and AI-oriented workloads. AMD presents performance comparisons for server workloads, including an AI-workload result, but Justice cautions that these figures do not predict desktop gaming performance.

Desktop implications and analysis

Justice sees the increase to 12 full Zen 6 cores per complex as a possible route to a 24-core, two-complex desktop processor. He stresses that this is only a possibility: AMD has not confirmed desktop core counts or whether it will use that configuration.

The video does not provide hands-on Zen 6 testing. Justice says desktop performance will depend on factors including clock speeds as well as architectural changes. It remains unknown whether Zen 6 will deliver a modest or more substantial improvement over Zen 5 in games.

Reviews, guides, and related material

• Architecture guide: A high-level walkthrough of AMD’s Zen 6 press slides, with commentary on the core design, instruction support, and server comparisons.
• Related video: Justice refers viewers to a separate video covering EPYC 9006 configurations and server-product marketing.
• Related review and comparison: He mentions an existing processor review and Zen 4-versus-Zen 5 testing on The FPS Review’s channel and website, using it as context for why Zen 6’s real-world desktop uplift remains uncertain.

Main speakers and sources

• Brent Justice, host of The FPS Review, provides the narration and analysis.
• AMD’s official Zen 6 / EPYC 9006 presentation slides are the primary source for the architectural details and performance claims.