Static Timing Analysis- II

Main Ideas and Lessons from the Lecture

• Purpose of Static Timing Analysis (STA): Understanding how STA works helps interpret tool results and make efficient design changes to fix or improve timing.

• STA path types: STA analyzes two main kinds of paths:

  1. Data paths
  2. Clock paths

Key Definitions (Data Path)

• Timing start points for a data path can be:

  • Input ports of the design, or
  • Clock pins (CP) of flip-flops

• Data path structure:

  • Starts at a timing start point
  • Traverses only combinational logic (no sequential elements like flip-flops)
  • Ends at timing end points

• Timing end points typically include:

  • D pins of flip-flops
  • Output ports (checked to ensure external downstream sampling flip-flops meet setup/hold)

Key Definitions (Clock Path)

• Clock path starts at the clock source as defined in constraints (SDC).
• It can traverse clock distribution elements (e.g., buffers/inverters; possibly clock-gaters).
• Clock path ends at the clock pins of flip-flops.

Example Circuit Interpretation

For a circuit with two flip-flops and input/output ports, the lecturer identifies:

• Multiple data paths (from input/FF clock pins through combinational logic to endpoints)
• Clock paths (clock source through the clock network to FF CP pins)

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Methodology / “Mechanism” of STA (Detailed Steps)

1) Build the Timing Graph

• STA converts the circuit into a timing graph (G = (V, E)):

  • Vertices (V): correspond to pins/ports in the circuit
  • Edges (E): represent timing arcs between pins/ports

• Two edge (arc) categories:

  • Cell arcs: timing arcs between pins of the same cell
  • Net arcs: timing arcs between pins of different cells directly connected by a net

• Edge annotations:

  • Each edge is annotated with delay (d_{ij})
  • Vertices may be annotated with timing-related quantities such as:
    • arrival time
    • required time
    • slack
    • and other related attributes

• Special vertices:

  • Source vertices: have no incoming edges (e.g., input ports, clock pins defined as clock start points)
  • Sink (sync) vertices: typically endpoints such as output ports or FF D pins where checks occur

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2) Compute/Annotate Edge Delays via a Delay Calculation Engine

• STA uses a delay calculator (built-in or coupled).
• Approach: decompose the design into smaller stages and compute delay per stage.

Stage definition

A stage consists of:

• a driving cell
• the interconnect/net it drives
• the driven pins (loads) it reaches

Delay calculator inputs/models it requires

1. Driver model from the Liberty (.lib) file

   • Delay model could be:
     • NLDM (Non-Linear Delay Model)
     • or advanced models like CCS/ECS

2. Interconnect model

   • Includes capacitance/resistance effects
   • Early flow may use simple approximations (e.g., ignore/interpolate), while later flow uses more accurate models
   • Typically based on extracted parasitics stored in SPEF (Standard Parasitic Exchange Format)

3. Receiver (sink) model

   • How each load pin responds (lumped or advanced receiver model)

4. Input waveform / slew

   • Delay depends on the slew/transition of the incoming signal

Waveform propagation requirement

• Delay is computed in topological order:
  • start from known source/port transitions
  • propagate to fan-out successors

Outputs of delay calculation

• Edge delay
• resulting slew at vertices
• sufficient data to compute arrival/required times downstream

Annotation step

• The computed delay (and slew-related info) is stored on the timing graph so later steps reuse it.

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3) Compute Arrival Time (Forward Traversal)

• Arrival time definition: the time when a signal settles at a vertex.
• STA uses this to perform setup/hold checks against required times.

Single incoming edge

[ a_j = a_i + d_{ij} ]

Multiple incoming edges

• Signals could potentially toggle multiple times; STA uses bounds to stay efficient by tracking:
  • minimum and maximum arrival time bounds

Conceptual arrival bound equations

• Minimum arrival bound: [ a_j^{min} = \min_i (a_i^{min} + d_{ij}) ]

• Maximum arrival bound: [ a_j^{max} = \max_i (a_i^{max} + d_{ij}) ]

Traversal property

• Arrival times are computed efficiently because a vertex is visited only once in forward propagation order (topological structure).

Extra complications discussed

• Rise vs. fall behavior: rise delay and fall delay differ, so a vertex can have up to four arrival values:
  • max rise, max fall
  • min rise, min fall
• Slew propagation: since delay depends on slew, slew must be propagated and stored at vertices.

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4) Compute Required Time (Backward Traversal)

• Required time definition: a time constraint used to avoid violations.
• It differs for:
  • Setup (late analysis): must arrive no later than the required time
  • Hold (early analysis): must not arrive too early (signal must arrive no earlier than the required time)

Setup required time behavior

• “Latest permissible arrival time”
• computed using min operations across output paths (more pessimistic bound)

Hold required time behavior

• “Earliest permissible arrival time”
• computed using max operations across output paths (more pessimistic bound)

Required time computation traversal

• Starts from endpoints/sinks (output ports, FF D pins) where required times come from constraints/clock period
• Propagates backward through the timing graph (reverse of fan-out)

Efficiency

• Like arrival time, required time can be computed in one traversal if output required times are already known.

Relation to clock

• Required times are primarily determined by clock constraints (e.g., clock period/frequency).

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5) Compute Slack and Determine Timing Safety

Setup slack (late analysis)

• Defined as: [ \text{Slack} = RT - AT ]

• Constraint: Slack must be positive to avoid setup violation.

Hold slack (early analysis)

• Defined as: [ \text{Slack} = AT - RT ]

• Constraint: Slack must be positive to avoid hold violation.

Interpretation

• Positive slack ⇒ timing safe with margin
• Negative slack ⇒ timing violation

Lecture example outcome

• Timing endpoints had positive slack in both cases ⇒ no timing violation.

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Speakers / Sources Featured

Speakers

• None explicitly named (only “the course lecturer” is implied).

Sources Cited

• The lecturer mentions “these books” at the end, but no specific titles or authors are provided.