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11 PCB Layout Rules to NEVER Break

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Overview

This video explains how two PCB designs with the same schematic can behave completely differently in real life—such as:

  • Passing vs. failing EMI tests
  • Random resets
  • Poor wireless range

The root cause is that PCB layout decisions change the underlying physics. The presenter shares 11 PCB layout rules to never break, including what to do instead, plus a mention of a free PCB layout checklist and their background in microchip design.

11 PCB Layout Rules (with “What to do instead”)

1) Never use via-in-pad without knowing the cost

Problem: Solder wicks into the via during assembly, starving the joint and risking weak/open connections. Fix: Place the via next to the pad and connect with a short trace. If required: Specify filled + capped vias in fab notes and budget extra cost.

2) Never design a board without test points

Problem: Boards without test points can’t be reliably tested in production (either unverified shipments or costly hand probing). Fix: Add test pads on:

  • Every power rail
  • Communication bus
  • Signals needed for programming/debugging

Benefit: Essential for leadless parts (QFNs/BGAs) where pins are underneath.

3) Never put copper under an antenna

Problem: Copper/ground close to an antenna detunes it and absorbs energy, reducing wireless range. Fix: Follow each antenna/module’s keep-out zone from its datasheet across all layers.

Also avoid: Metal standoffs/screws near the antenna (same detuning effect). Compliance note: Pre-certified wireless modules only remain certified when used per datasheet.

4) Never place decoupling capacitors far from the pin

Problem: Distance adds inductance, preventing the cap from handling fast current spikes → glitches/resets. Fix: Place decoupling caps very close to the IC power pins. Use short/wide connections and add ground vias right at the cap pads.

5) Never route differential pairs like ordinary traces

Problem: Differential links (USB/Ethernet/HDMI) only cancel noise if layout is correct. Fix: Maintain:

  • Matched trace lengths
  • Controlled impedance
  • An unbroken reference plane
  • No stubs

Recommendation: Use PCB tools for proper differential-pair routing.

6) Never ignore the switching regulator hot loop

Problem: The high di/dt current loop acts like a tiny antenna; larger loop area emits more noise. Fix: Use the datasheet-recommended layout, place the input capacitor as close as possible to the regulator, and keep the loop on a single layer.

7) Never leave the board without stitching vias

Problem: Without ground stitching vias, plane gaps act like slots that leak radiation; ground return paths on different layers take longer routes. Fix: Add ground stitching vias across the board, especially around:

  • Edges
  • High-speed routing
  • RF/antenna feed lines

8) Never run high-speed traces near the board edge

Problem: Near edges, electric fields fringe outside the ground plane boundary and radiate like antennas → EMI failures. Fix: Keep fast signals away from the edge by ~4–5× the trace-to-ground-plane spacing (often ~1 mm or more) and route on inner layers when possible.

9) Never skip a thermal path for hot components

Problem: Layout can cause regulators/components to brown out after heating; many use a bottom power/thermal pad that needs a heat path. Fix: Follow the component datasheet landing pattern, including the recommended via array (thermal vias are generally acceptable) and provide as much copper area as possible.

10) Never starve a power trace or via

Problem: Too-thin power conductors or vias cause voltage drop, overheating, and potential failures—possibly leading to resets under high load. Fix: Size power traces for worst-case current with margin using calculators.

For higher currents: Use thicker copper (e.g., copper pours) and multiple vias in parallel when changing layers.

11) Never route signals across a plane split

Problem: A plane split forces return current to detour around the gap, creating a large radiating loop → EMI + hard-to-reproduce glitches. Fix: Reroute traces so they don’t cross gaps in the plane beneath them.

Note: Plane splits can be valid (e.g., analog isolation), but the rule applies to routing over them.

Extra Tools / Resources Mentioned

  • A free PCB layout checklist covering the 11 rules (linked in description / via QR code)
  • A layout review service through the presenter’s hardware academy to catch issues before fabrication

Main Speaker / Source

John Teal — presenter; ex-microchip design engineer at Texas Instruments and founder of hardware academy.

Original video