PROGRAMMABLE LOGIC DEVICES (PLDs)

What Programmable Logic Devices (PLDs) Are

The lesson contrasts fixed-logic devices with programmable logic devices (PLDs). A design built from separate, fixed-function integrated circuits can require many components and complicated interconnections. A PLD combines logic resources on a single chip and can be programmed for a particular application, reducing board space and making designs easier to revise.

Why PLDs Are Useful

The instructor lists these advantages:

• Less design time and reduced circuit space
• Lower power requirements and production costs
• Flexible designs that can be reprogrammed for different requirements
• High design security and switching speed
• Software tools to help create, verify, and revise designs

Classification of PLDs

The lesson identifies three main types:

1. SPLD — Simple Programmable Logic Device

   • An earlier, simpler class of programmable devices, suited to smaller circuits and limited logic functions.
   • A low-cost option that may still be useful for simple applications.
   • Its subtypes are:
     • PROM (Programmable Read-Only Memory): Fixed AND array and programmable OR array.
     • PAL (Programmable Array Logic): Programmable AND array and fixed OR array.
     • PLA (Programmable Logic Array): Both AND and OR arrays are programmable.

2. CPLD — Complex Programmable Logic Device

   • A reprogrammable device built from multiple SPLD-like logic blocks on one chip.
   • The lesson says it is programmed using VHDL and refers to memory technologies, though the specific terms in the subtitles are unclear.

3. FPGA — Field-Programmable Gate Array

   • Intended for more complex applications.
   • Can contain thousands to millions of logic gates and provides extensive system interconnection resources.

PLD Design Flow

The instructor presents a general design flow for CPLDs and FPGAs:

1. Design entry: Enter the application’s specifications using a suitable method, such as schematic entry, a hardware description language (HDL), a finite-state machine (FSM), or EDIF.
2. Synthesis: Translate the high-level design description into a lower-level circuit representation. Syntax errors, such as errors in HDL code, must be corrected.
3. Functional simulation: Check whether the design behaves according to the intended specifications.
4. Review and correction: If simulation reveals errors, return to the design-entry stage, revise the specifications or design, and repeat the process.
5. Design implementation: Once the design is judged correct, implement the application in the target programmable device.

Design Approaches

The lesson describes three ways to organize a design:

• Top-down: Begin with the overall system and repeatedly divide it into smaller subsystems and components. The instructor recommends this approach for larger systems.
• Bottom-up: Start with known low-level components or devices and combine them into progressively larger parts of the design.
• Mixed: Combine both approaches—for example, start with top-down design and use bottom-up methods at lower levels.

Speakers and Sources

• Instructor/narrator: A single speaker presents the lesson; the speaker’s name is not stated in the subtitles.
• Source/channel: Prof. Barapate’s Tutorials