Apple A20 Pro Chip Deep-Dive

Summary

The video analyzes Apple’s A20 Pro using high-resolution die shots produced by the STEEL team. It presents the chip as an evolutionary design whose gains come from several factors working together: TSMC’s N2 process, a new memory-packaging approach, more cache and compute resources, and improved thermal headroom.

Packaging and cooling

• The A20 Pro is described as the first commercially available chip made on TSMC’s N2 process, which introduces Gate-All-Around (GAA) nanosheet transistors.
• Its major packaging change is Wafer-Level Multi-Chip Module (WMCM). Unlike earlier iPhone chips using InFO-PoP, which stacked DRAM on top of the SoC, WMCM places DRAM beside it.
• The analysis argues that this gives heat a more direct path to the vapor chamber, helping manage peak power. It also positions the design for future, potentially faster memory.
• The video frames packaging as a response to rising thermal demands: sustained power remains constrained by a phone’s cooling capacity, while peak power has increased substantially.

Die size and TSMC N2

• The A20 Pro die is measured at about 99.5 mm² including scribe lines, roughly the same size as the A19 Pro.
• Despite the similar area, the A20 Pro reportedly adds faster CPU cores, one GPU core, more SLC, twice the NPU cores, and a 50% wider memory interface.
• The die-shot analysis identifies three nanosheets per transistor stack on N2, compared with four on Intel 18A. The narrator notes that more sheets can provide greater drive current but also increase capacitance and manufacturing complexity; three are presented as a suitable trade-off for a smartphone chip.
• N2 is said to improve logic density over TSMC N3P, while SRAM remains about the same size. The video also points out that different CPU clusters use different cell-library characteristics.

Floorplan and connectivity

• The memory interface is divided into three sections, each with two 16-bit links, for 96 bits total. At LPDDR5X-9600, the narrator calculates bandwidth of 115.2 GB/s, 50% above the A19 Pro. The increase comes from a wider interface.
• A camera PHY appears to serve the rear-camera system. Other visible connections include a likely PCIe PHY, two display PHYs, and a USB-related high-speed PHY. The second display PHY doubles display I/O compared with the A19 Pro, which the narrator connects to the two-screen iPhone Duo design.
• The die appears to lack the MIPI PHY found on earlier iPhone SoCs, which the narrator says was used for the front-facing camera and infrared sensors. How those components connect remains unresolved in the analysis.

CPU, cache, GPU, and neural engine

• The two S-cores are described as using the same CPU IP generation as the M6, ahead of the M5 generation. They share 16 MB of L2 cache and have a dedicated AMX cluster for machine-learning acceleration. The narrator notes that, unlike some newer S-cores, these do not appear to have an additional L2 slice.
• Four E-cores share 8 MB of L2 cache, up from 6 MB on the A19 Pro and 4 MB on the A18 Pro. The shared S-core cache remains at 16 MB.
• The System Level Cache (SLC) is split into 12 MB and 24 MB clusters, totaling 36 MB, 4 MB more than on the A19 Pro.
• The GPU has seven physical cores and a shared 2 MB L2 cache. Its placement near the SLC and memory interface is noted as advantageous for accessing cache and bandwidth.
• The new dual 16-core Apple Neural Engine is described as having 16 visible cores in the die shot, compared with eight visible cores on the previous 16-core design. It occupies roughly 60% more area than the A19 Pro’s NPU while also doubling its core count.

Overall assessment

The narrator characterizes the A20 Pro as an evolution rather than a revolution. Its most notable architectural changes are the wider memory interface and doubled NPU, alongside CPU, GPU, and cache increases. The video argues that N2 density and efficiency let Apple add these features without substantially increasing die size, while WMCM and a larger vapor chamber improve thermal headroom. Taken together, these changes make the upgrade more significant than the component changes alone might suggest.

Reviews, guides, or tutorials: This is a silicon deep-dive and die-shot analysis rather than a hands-on product review or step-by-step tutorial.

Main speaker and sources: The video’s narrator, from the High Yield channel, provides the analysis. The die shots are credited to the STEEL team; the video also references SemiAnalysis STEEL.