8086 microprocessor | Minimum mode | Lec-22 | Bhanu Priya

Main ideas / concepts explained

Minimum mode vs. maximum mode selection (8086/8088 family)

• The 8086 (and sometimes the 8088) can operate in either minimum mode or maximum mode.
• The operating mode is determined by the status of the MN/ MX̅ (MN by MX bar) signal:
  • MN/ MX̅ = 1 (logic 1) → Minimum mode
  • MN/ MX̅ = 0 (logic 0) → Maximum mode
• The MN/ MX̅ signal indicates whether the CPU should act as a master controller of the system bus (minimum mode) or rely on additional bus-control hardware (maximum mode).

Why minimum mode exists (system structure)

• Minimum mode is used in small systems, typically when there is:
  • Only one processor / one CPU subsystem (single processor system).
• In this configuration, the 8086 itself provides/generates the control signals, acting as the master controller of the system bus.

Role of external components shown in the minimum mode structure

External “glue logic” components commonly referenced include:

• Clock generator
• Latches / transceivers
• Memory and I/O devices with decoding logic
• A 3-to-8 decoder to generate control signals for memory/I/O operations
• Interrupt lines and DMA-related handshaking signals

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Methodology / instruction-like explanation (pin/control signal workflow)

1) Decide the CPU operating mode

• Check MN/ MX̅:
  • If MN/ MX̅ is logic 1 → minimum mode
  • If MN/ MX̅ is logic 0 → maximum mode

2) Understand the bus separation using ALE and latches

• The 8086 uses address/data multiplexing, separated using:
  • ALE (Address Latch Enable) from the 8086 to external latches.
• When ALE is asserted (ALE = 1):
  • The multiplexed address is latched and appears on the address bus
  • The multiplexed data appears on the data bus (through transceivers)

3) Address bus latching (20-bit address using 8-bit latches)

• The 8086 generates a 20-bit address.
• The external design uses three 8-bit latches to handle the 20-bit address:
  • 8-bit latch size × 3 latches = 24 bits capability, sufficient to cover 20-bit addressing
• Three latches are required due to the 20-bit address width.

4) Data bus buffering using transceivers (16-bit data)

• The 8086 has a 16-bit data bus.
• Data is buffered via two 8-bit transceivers:
  • 8-bit + 8-bit = 16-bit total
• Two key transceiver control signals determine communication direction and enabling:

a) DEN (Data Enable)

• Controls whether the transceiver is enabled for communication.

b) DT/ R̅ (Transmit/Receive)

• Determines direction:
  • DT/ R̅ = 1 (“high”) → transmit
  • DT/ R̅ = 0 (“low/0̅”) → receive

c) Combined behavior (conceptually described)

• Based on DEN̅ and DT/ R̅, the transceivers are either:
  • Disabled, or configured so the CPU sends data or receives data.

5) Generate memory vs I/O control signals using a decoder

• A 3-to-8 decoder is driven using control lines / address-related inputs.
• It generates and/or uses control signals such as:
  • M/IO̅
  • RD̅ (read)
  • WR̅ (write)
• The resulting operations are:
  • Memory Read
  • Memory Write
  • I/O Read
  • I/O Write
• These signals activate the appropriate memory and I/O devices.

6) Interrupt and DMA-related signals in minimum mode

Interrupt inputs

• Interrupt lines described include:
  • NMI, INTR, INTA
• When an external device needs CPU interaction, these lines can be activated.
• NMI is described as non-maskable (higher priority), serviced only after completing the current instruction.

DMA / bus request handshaking

• Hold and Hold Acknowledge relate to DMA controller operation.
• DMA requests use HOLD:
  • the CPU grants bus control after acknowledging via Hold Acknowledge.

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Main lessons

• Minimum mode occurs when MN/ MX̅ = 1.
• It targets single-processor / simpler systems, where the CPU generates control signals.
• Key roles of external glue logic:
  • ALE + latches: separate multiplexed address/data
  • Transceivers + DEN/DT-R: manage data direction and enabling
  • Decoder: create correct memory/I/O read/write control signals
  • Interrupt and DMA lines: manage asynchronous events and bus ownership transfer

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Speakers / sources featured

• Bhanu Priya (the instructor speaking)